MCU decoupling: layout details that matter more than “100 nF per pin”

Draw the transient-current loop first

When internal logic switches, an MCU draws short current pulses at its supply pins. The path to minimize is the complete loop through the VDD pin, decoupling capacitor, and ground return—not merely the straight-line distance to a power plane.

Place each capacitor beside the supply pin it serves and put the ground via next to its pad. If a layer change is unavoidable, keep the power and ground connections short and geometrically balanced.

100 nF is not a universal answer

Nominal capacitance describes only the low-frequency side. Package, pads, traces, and vias add inductance that sets the self-resonant frequency; above it, the capacitor behaves increasingly like an inductor.

A practical network often combines several small-package 100 nF capacitors with 1 µF to 10 µF local bulk capacitance. Confirm the final mix against the device datasheet, target impedance, and board-level simulation or measurement.

Rules of thumb are useful starting points, but reducing layout inductance usually matters more than changing 100 nF to 220 nF.

Verify with a scope, not intuition

Observe the rail in the worst operating mode, with fast interfaces, timers, and high-current GPIO active together. Use a ground spring; a long probe ground can create high-frequency spikes that are not present on the board.

Look beyond peak-to-peak ripple. Check whether resets, ADC errors, or communication faults align with supply transients, then freeze the capacitor count and BOM.